mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 (3.556) (0.5) (1.656) (3.556) (6.25) (0.75) (30.5) (1.778) (1.778 26) (6.25) (6.25) 16 17 18 13 14 15 10 987 654 321 11 12 19 20 21 22 23 24 35 34 33 32 31 26 25 27 28 29 30 (8) (8) (5) (0.5) (17.4) (17.4) (0.5) (1.25) (2.5) (1.2) (35 ) a (6.5) (10.5) (1) pcb terminal terminal code 1 vufs 2 (upg) 3 vufb 4 vp1 5 (com) 6 up 7 vvfs 8 (vpg) 9 vvfb 10 vp1 11 (com) 12 vp 13 vwfs 14 (wpg) 15 vwfb 16 vp1 17 (com) 18 wp 19 (ung) 20 vno(nc) 21 un 22 vn 23 wn 24 fo 25 cfo 26 cin 27 vnc 28 vn1 29 (wng) 30 (vng) 31 p 32 u 33 v 34 w 35 n pattern slit (pcb layout) (1) (1.9) (0.5) (1.5) (1.8min) (0.5) (1) heat sink side type name , lot no. dummy pin ( 2 depth 2) ( 3.3) heat sink side detail a *note2 (7.62 4) (7.62) (41) (42) (49) (4min) *note1:(***) = dummy pin. *note 2: in order to increase the surface distance between terminals, cut a slit, etc. on the pcb surface when mounting a module. PS21542-N integrated power functions 600v/5a low-loss 4th generation (planar) igbt inverter bridge for 3 phase dc-to-ac power conversion. application ac100v~200v inverter drive for motor control. fig. 1 package outlines mitsubishi semiconductor PS21542-N transfer-mold type insulated type integrated drive, protection and system control functions for upper-leg igbt s : drive circuit, high voltage isolated high-speed level shifting, control circuit under-voltage (uv) protection. note : bootstrap supply scheme can be applied. for lower-leg igbt s : drive circuit, control circuit under-voltage protection (uv), short-circuit protection (sc). fault signaling : corresponding to a sc fault (low-side igbt) or a uv fault (low-side igbt). input interface : 5v line cmos/ttl compatible, schmitt trigger receiver circuit. dimensions in mm
mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 z drive circuit cbu cbu+ cbv cbv+ cbw cbw+ (15v line) (5v line) (note 1, 2) v d v nc v nc w ac input ac line output v u input signal coditioning level shifter drive circuit protection circuit (uv) input signal coditioning input signal coditioning input signal conditioning fo logic sc protection protection circuit (uv) protection circuit (uv) control supply under-voltage protection drive circuit drive circuit f o cfo p n 1 n f o output (5v line) (note 3, 5) high-side input (pwm) (5v line) (note 1,2) low-side input (pwm) m (note 6) dip-ipm c c4 c3 c3 : tight tolerance, temp-compensated electrolytic type c4 : 0.22~2 f r-category ceramic capacitor for noise filtering. (note : the capacitance value depends on the pwm control scheme used in the applied system). note1: to prevent the input signals oscillation, an rc coupling at each input is recommended. (see also fig. 6) 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to cpu terminals without any opto-coupler or transformer isolation is possible. (see also fig. 6) 3: this output is open collector type. the signal line should be pulled up to the positive side of the 5v power supply with a pproximately 5.1k ? resistance. (see also fig. 6) 4: the wiring between the power dc link capacitor and the p/n1 terminals should be as short as possible to protect the dip-ipm against catastrophic high surge voltages. for extra precaution, a small film type snubber capacitor (0.1~0.22 f, high voltage type) is recommended to be mounted close to these p and n1 dc power input terminals. 5: fo output pulse width should be decided by connecting external capacitor between cfo and v nc terminals. (example : c fo =22nf t fo =1.8ms (typ.)) 6: high voltage (600v or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. l-side igbt s cin (note 4) fig. 3 inrush current limiter circuit level shifter level shifter h-side igbt s z : znr (surge absorber) c : ac filter (ceramic capacitor 2.2~6.5nf) (note : additionally, an appropriate line to line surge absorber circuit may become necessary depending on the application environment.) note1: in the recommended external protection circuit, please select the rc time constant in the range 1.5~2.0 s. 2: to prevent erroneous protection operation, the wiring of a, b, c should be as short as possible. drive circuit drive circuit protection circuit w v u b c v nc cin a p n1 n c r shunt resistor external protection circuit dip-ipm l-side igbt s h-side igbt s sc protection trip level i c (a) 2 0 short circuit protective function (sc) : sc protection is achieved by sensing the l-side dc-bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the rc circuit). when the sensed shunt voltage exceeds the sc trip-level, all the l-side igbts are turned off and a fault signal (fo) is output. since the sc fault may be repetitive, it is recommended to stop the system when the fo signal is received and check the fault. collector current waveform t w ( s) (note 1) (note 2) fig. 2 internal functions block diagram (typical application example) fig. 3 external part of the dip-ipm protection circuit
mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 p u v w n c control terminals fwd chip al board temp. measurement point (inside the al board) 16mm 18mm igbt chip power terminals temp. measurement point (inside the al board) groove al board specifications: dimensions 100 100 10mm, finishing: 12s, warp: 50~100 m 100~200 m of evenly applied silicon-grease igbt/fwd chip 400 20~+100 40~+125 2500 v d = v db = 13.5~16.5v, inverter part t j = 125 c, non-repetitive, less than 2 s (note 2) 60hz, sinusoidal, 1 minute, connection pins to heat-sink plate v cc(prot) t f t stg v iso v v v v ma v 20 20 0.5~v d +0.5 0.5~v d +0.5 15 0.5~v d +0.5 applied between v p1 -v nc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs applied between u p , v p , w p -v nc , u n , v n , w n -v nc applied between f o -v nc sink current at f o terminal applied between cin-v nc control supply voltage control supply voltage input voltage fault output supply voltage fault output current current sensing input voltage v d v db v cin v fo i fo v sc 450 500 600 5 10 20 20~+150 applied between p-n applied between p-n t f = 25 c t f = 25 c, instantaneous value (pulse) t f = 25 c, per 1 chip (note 1) v cc v cc(surge) v ces i c i cp p c t j condition symbol parameter ratings unit supply voltage supply voltage (surge) collector-emitter voltage each igbt collector current each igbt collector current (peak) collector dissipation junction temperature v v v a a w c maximum ratings (t j = 25 c, unless otherwise noted) inverter part condition symbol parameter ratings unit control (protection) part symbol ratings unit self protection supply voltage limit (short-circuit protection capability) heat-fin operation temperature storage temperature isolation voltage v c c v rms total system note 1 : the maximum junction temperature rating of the power chips integrated within the dip-ipm is 150 c (@ t f 100 c). however, to ensure safe operation of the dip-ipm, the average junction temperature should be limited to t j(ave) 125 c (@ t f 100 c). parameter condition note 2 : t f measurement point
mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 note 4 : short-circuit protection operates only at the low-arms. please select the value of the external shunt resistor such that the sc trip level is less than 8.5a 5: fault signal is outputted when the low-arm short-circuit or control supply under-voltage protective functions operate. the faul t output pulse-width t fo depends on the capacitance value of c fo according to the following approximate equation. : c fo = (12.2 ? 10 -6 ) ? t fo [f] condition symbol parameter limits inverter igbt part (per 1/6 module) (note 3) inverter fwd part (per 1/6 module) (note 3) r th(j-f)q r th(j-f)f min. c/w c/w thermal resistance typ. max. 6.0 6.5 unit junction-to-heat sink thermal resistance note 3 : grease with good thermal conductivity should be applied evenly about +100 m~+200 m on the contact surface of a dip-ipm and a heat sink. 8.5 1.0 9.7 1.0 0.9 1.8 0.53 12.0 12.5 12.5 13.0 2.0 4.0 4.9 0.8 0.43 10.0 10.5 10.3 10.8 1.0 0.8 2.5 applied between: u p , v p , w p -v nc , u n , v n , w n -v nc trip level reset level trip level reset level total of v p1 -v nc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs total of v p1 -v nc , v n1 -v nc v ufb -v ufs , v vfb -v vfs , v wfb -v wfs circuit current condition symbol parameter limits i d v foh v fol v fosat v sc(ref) uv dbt uv dbr uv dt uv dr t fo v th(on) v th(off) min. typ. max. unit control (protection) part v d = v db =15v v cin = 5v v d = v db =15v v cin = 0v v sc = 0v, f o = 10k ? 5v pull-up v sc = 0v, i fo = 1.5ma v sc = 1v, i fo = 15ma t j = 25 c, v d = 15v (note 4) fault output voltage short-circuit trip level supply circuit under-voltage protection t j 125 c fault output pulse width on threshold voltage off threshold voltage c fo = 22nf (note 5) 0.6 1.2 0.48 1.8 1.4 3.0 ma ma v v v v v v v v ms v v 2.15 2.25 3.00 1.35 0.65 1.65 1.3 1 10 ma v t j = 25 c t j = 125 c i c = 5a, t j = 25 c i c = 5a, t j = 125 c v ce(sat) v ec t on t rr t c(on) t off t c(off) i ces t j = 25 c, i c = 5a, v cin = 5v condition symbol parameter limits min. typ. max. 0.40 unit electrical characteristics (t j = 25 c, unless otherwise noted) inverter part collector-emitter saturation voltage fwd forward voltage v d = v db = 15v v cin = 0v switching times v cc = 300v, v d = v db =15v i c = 5a, t j = 125 c inductive load (upper-lower arm) v cin = 5 ? 0v collector-emitter cut-off current v ce = v ces 1.55 1.65 2.20 0.90 0.20 0.40 1.2 0.6 v s s s s s
mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 supply voltage control supply voltage control supply voltage control supply variation arm shoot-through blocking time pwm input frequency input on voltage input off voltage 400 16.5 16.5 1 v cc v d v db ? v d , ? v db t dead f pwm v cin(on) v cin(off) applied between p-n applied between v p1 -v nc , v n1 -v nc applied between v ufb -v ufs , v vfb -v vfs , v wfb -v wfs for each input signal t j 125 c, t f 100 c applied between u p , v p , w p -v nc , u n , v n , w n -v nc condition symbol parameter limits min. typ. max. 0 13.5 13.5 1 1.5 unit recommended operation conditions 300 15.0 15.0 5 v v v v/ s s khz v v 0~0.65 4.0~5.5 dip-ipm + heat-sink heat-sink measurement range 3mm + note 6: measurement point of heat-sink flatness mounting screw : m3 weight 9.8n weight 4.9n. 90deg bend (note 6) condition parameter limits mounting torque terminal pulling strength bending strength weight heat-sink flatness min. mechanical characteristics and ratings typ. max. 0.59 10 2 50 unit 0.78 20 0.98 100 n m s times g m eiaj-ed-4701 eiaj-ed-4701
mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 fig. 4 the dip-ipm internal circuit note: the igbts gates and the hvics com terminals are connected to the dummy pins. dip-ipm u out v out w out v no cfo gnd fo w n v n u n v cc hvic 3 hvic 2 hvic 1 igbt1 igbt2 igbt3 igbt4 igbt5 igbt6 di6 di5 di4 di3 di2 di1 lvic cfo cin cin n w v u p ho in com v b v s v cc ho in com v b v s v cc ho in com v b v s v cc fo w n v n u n v p v p u p v nc v n1 v p1 v p1 v p1 v wfs v vfs v ufs v wfb v vfb v ufb v no(nc)
mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 fig. 5 timing charts of the dip-ipm protective functions [a] short-circuit protection (n-side only) (for the external shunt resistor and cr connection, please refer to fig. 3.) a1. normal operation : igbt on and carrying current. a2. short-circuit current detection (sc trigger). a3. igbt gate interrupt. a4. igbt turns off. a5. f o timer operation starts : the pulse width of the f o signal is set by the external capacitor c fo . a6. input h : igbt off state. a7. input l : igbt on state. a8. igbt off state. [b] under-voltage protection (n-side, uv d ) b1. normal operation : igbt on and carrying current. b2. under-voltage trip (uv dt ). b3. igbt off in spite of control input condition. b4. f o timer operation starts. b5. under-voltage reset (uv dr ). b6. normal operation : igbt on and carrying current. b6 b1 b3 b5 b2 reset uv dt uv dr set b4 fault output fo output current ic control supply voltage v d protection circuit state control input a5 a8 a4 a3 a1 a2 sc reset set a7 a6 fault output fo sense voltage of the shunt resistor sc reference voltage cr circuit time constant delay output current ic internal igbt gate protection circuit state n-side control input
mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 [c] under-voltage protection (p-side, uv db ) c1. control supply voltage rises : after the voltage level reachs uv dbr , the circuits start to operate when the next input is applied. c2. normal operation : igbt on and carrying current. c3. under-voltage trip (uv dbt ). c4. igbt off in spite of control input condition (there is no f o signal output). c5. under-voltage reset (uv dbr ). c6. normal operation : igbt on and carrying current. fig. 6 recommended cpu i/o interface circuit note : rc coupling at each input (parts shown dotted) may change depending on the pwm control scheme used in the application and on the wiring impedance of the application s printed circuit board. cpu 4.7k ? 5.1k ? 1nf 1nf u p ,v p ,w p ,u n ,v n ,w n v nc (gnd) fo dip-ipm 5v line c6 c1 c2 c4 c5 c3 reset uv dbt uv dbr set reset fault output fo output current ic control supply voltage v db protection circuit state control input high-level (no fault output)
mitsubishi semiconductor PS21542-N transfer-mold type insulated type sep. 2001 fig. 7 typical dip-ipm application circuit example note 1 : to prevent the input signals oscillation, an rc coupling at each input is recommended, and the wiring of each input should be a s short as possible (less than 2cm). 2: by virtue of integrating an application specific type hvic inside the module, direct coupling to cpu terminals without any opto -coupler or transformer isolation is possible. 3: f o output is open collector type. this signal line should be pulled up to the positive side of the 5v power supply with approxima tely 5.1k ? resistance. 4: f o output pulse width should be decided by connecting an external capacitor between cfo and v nc terminals (c fo ). (example : c fo = 22 nf t fo = 1.8 ms (typ.)) 5: each input signal line should be pulled up to the positive side of the 5v power supply with approximately 4.7k ? resistance (other rc coupling circuits at each input may be needed depending on the pwm control scheme used and on the wiring impedances of the system s printed circuit board). approximately a 0.22~2 f by-pass capacitor should be used across each power supply connection terminals. 6: to prevent errors of the protection function, the wiring of a, b, c should be as short as possible. 7: in the recommended protection circuit, please select the r 1 c 5 time constant in the range of 1.5~2 s. 8: each capacitor should be put as nearby the terminals of the dip-ipm as possible. 9: to prevent surge destruction, the wiring between the smoothing capacitor and the p&n1 terminals should be as short as possible. ap- proximately a 0.1~0.22 f snubber capacitor between the p&n1 terminals is recommended. ho ho dip-ipm c3 c3 c3 c3 c2 c2 c2 c1 c1 c1 ho in in in com com com u out v out w out v no cfo gnd f o w n v n v cc c b a c4(c fo ) cfo r1 c5 cin cin n1 n w v u p v s v s v s v b v b v b v cc v cc v cc fo w n v n u n u n w p v p u p v nc v n1 v p1 v p1 v p1 hvic1 hvic2 hvic3 lvic v wfs v vfs v ufs v wfb v vfb v ufb m shunt resistor the long wiring of gnd might generate noise on input signals and cause igbt to be malfunctioned. if this wiring is too long, the sc level fluctuation might be large and cause sc malfunction. if this wiring is too long, short circuit might be caused. 15v line 5v line u n i t c p u 5v line c1: tight tolerance temp - compensated electrolytic type; c2,c3: 0. 22~2 f r - category ceramic capacitor for noise filtering
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